Ferroelectric thin films have been used in nonvolatile memory devices to form ferroelectric memory devices. Ferroelectric memory devices utilize the spontaneous polarization phenomenon of a ferroelectric material to store information. High speed read/write operations may be accomplished with ferroelectric memory devices compared to conventional Erasable and Programmable Read Only Memories (EPROM) or Electrically Erasable and Programmable Read Only Memories (EEPROM).
Moreover, if a ferroelectric thin film is used as a dielectric layer in a cell capacitor of a Dynamic Random Access Memory (DRAM), a refresh operation may not be required, which can thereby reduce the power consumption of the DRAM and can improve the speed thereof. A ferroelectric memory device can perform read and write operations using a single power supply voltage similar to a Random Access Memory (RAM). Accordingly, ferroelectric memory devices are referred to as Ferroelectric RAM (FRAM) devices.
FRAM devices may be classified into two categories based on the unit cells thereof. The first category includes devices having unit cells including a transistor in which the ferroelectric film is used as a gate insulating layer. The second category includes unit cells having an access transistor and a capacitor in which the ferroelectric film is used for the dielectric layer thereof.
A FRAM in the first category, including a ferroelectric film as a gate insulating layer in a transistor, may have operational problems. For example, a silicon dioxide layer may be generated at the interface between a silicon substrate and the ferroelectric film which functions as a gate insulator via a reaction between the silicon substrate and oxygen atoms. Moreover, it may be difficult to obtain high quality ferroelectric films due to the lattice constant difference or thermal expansion coefficient difference between the silicon substrate and the ferroelectric film.
For at least these reasons, FRAM devices of the second category have also been developed, in which the ferroelectric film is used as the dielectric layer of a cell capacitor. These devices may generally have a similar structure to a cell structure of a DRAM.
FIG. 1 is an equivalent circuit diagram of a conventional unit cell of a FRAM in which the ferroelectric film is used as the dielectric layer of the cell capacitor. In the circuit configuration shown in FIG. 1, the gate electrode G of an NMOS transistor T is connected to a word line W. The drain region D is connected to a bit line B, and the source region S is connected to one electrode of a ferroelectric capacitor C. The other electrode of the ferroelectric capacitor C is connected to a plate line P.
FIG. 2 is a cross-sectional view of a conventional FRAM unit cell. As shown in FIG. 2, the conventional FRAM unit cell includes a semiconductor substrate 1 doped with P-type impurities, a field oxide layer 6, a gate electrode 3, a source region 14, a drain region 5, a first InterLayer Dielectric (ILD) film 7, a lower electrode 8, a ferroelectric layer 9, a second ILD film 13, an upper electrode 10 and a bit line B covering the drain region 5. The field oxide layer 6 is formed on the semiconductor substrate 1, to define an active region and an inactive region, and the gate electrode 3 is formed in the active region. The source and drain regions 14 and 5 are formed in the active region, at opposite sides of the gate electrode 3, by doping N-type impurity.
The first ILD film 7 exposes the source region 14 and the drain region 5, and covers the gate electrode 3 and the field oxide layer 6. The lower electrode 8 is formed of platinum (Pt) on a region of the first ILD film 7 formed on the field oxide layer 6 adjacent to the source region 14. The ferroelectric layer 9 on the lower electrode 8 is formed of PZT (PbZr.sub.x Ti.sub.1-x O.sub.3).
The second ILD film 13 is formed on the first ILD film 7 while exposing the ferroelectric layer 9, and the upper electrode 10 is formed of a metal wiring which connects the source region 14 exposed by the first ILD film 7 to the ferroelectric layer 9 exposed by the second ILD film 13. A borophosphosilicate glass (BPSG) layer is conventionally used for the first and second ILD films 7 and 13.
In FIG. 2, the gate electrode 3, the drain region 5 and the source region 14 form an access transistor T. The lower electrode 8, the ferroelectric layer 9 and the upper electrode 10 form a capacitor C. The lower electrode 8 acts as the plate line P of FIG. 1, and the gate electrode 3 acts as the word line W of FIG. 1.
In the conventional FRAM unit cell having the above-described structure, the lower electrode 8 made of Pt directly contacts the first ILD film 7 made of BPSG. The Pt layer may tend to lift off due to the weak adhesion between the Pt layer and the BPSG layer. Also, lead (Pb) or titanium (Ti) atoms in the ferroelectric layer 9 may pass through the Pt layer to diffuse into the first ILD film 7. Accordingly, the characteristics of the ferroelectric layer 9 may degrade, and thereby degrade the performance of the FRAM unit cell.
Finally, the first and second ILD films are generally etched to expose the source region 14 and the ferroelectric layer 9. As shown in FIG. 2, the ILD film formed on the ferroelectric layer 9 is thinner than the ILD films formed on the source region 14. Thus, in order to expose the source region 14 after the ferroelectric layer 9 is exposed, overetching may be required. Accordingly, the characteristics of the ferroelectric layer 9 may degrade due to the etch damage therein.